1. The Field of the Invention
The present invention relates to split-gate memory cells of the type utilizable in an erasable programmable read-only memory (EPROM) and, more particularly, to a split-gate memory cell that is fabricated utilizing stacked etch techniques, but which is immune to bit line interruption and bit line to bit line reach-through.
2. Discussion of the Prior Art
FIG. 1A shows a conventional stacked gate EPROM cell 10. The EPROM cell 10 includes a buried N+ source region 12 and a buried N+ drain region 14 formed in a P- silicon substrate 16 and separated by a substrate channel region 18. Overlying channel region 18 is a layer of insulating material 20, typically silicon dioxide. A floating gate 22 is formed on the insulating material 20. Typically, floating gate 22 is formed of polycrystalline silicon. Overlying floating gate 22 is a second layer 24 of insulating material, typically a composite of oxide/nitride/oxide (ONO). A control gate 26 is formed on the ONO layer 24. Typically, the control gate 26 is also formed of polycrystalline silicon.
A plan view of the stacked gate EPROM cell 10 is shown in FIG. 1B. The structure of the cell 10 derives its "stacked-gate" designation because of the self-aligned etching process which is utilized to form the vertically-aligned control gate line 26 and floating gate 22 of the cell 10.
The processing sequence for forming the polysilicon floating gate 22 and the polysilicon control line 26 of the stacked gate cell 10 is as follows. Referring to FIG. 1A, first, a layer of polysilicon is formed on the intermediate layer of silicon dioxide 20. The polysilicon layer and the underlying oxide 20 are then masked and etched to define the floating gate 22. The edges of the floating gate 22 are then utilized in a self-aligned implant step to form the buried N+ source and drain regions 12 and 14, respectively. Next, an ONO layer is grown over the entire structure. This is followed by growth of a second polysilicon layer from which the control gate line 26 will be formed. The second polysilicon layer is then masked and etched. The resulting control gate line 26 is then used as a self-aligned mask to etch the interpoly ONO 24 and the underlying floating gate 22 to define the final structure of the stacked gate cell 10 shown in FIG. 1A.
More recently, split-gate EPROM cells have been proposed as a means for improving on the packing density and yield of the above-described stacked gate EPROM cell.
U.S. Pat. No. 4,639,893, issued Jan. 27, 1987 to Boaz Eitan discloses an implementation of a split-gate EPROM cell. Referring to FIG. 2A, the split-gate memory cell 30 disclosed by Eitan is formed by a process which self-aligns the drain region 32 to an edge of the floating gate 34. The floating gate 34 extends only over a first section 35 of the channel region 36 between the drain region 32 and the source region 38, thereby defining a second section 37 of the channel region between the floating gate 34 and the source region 38. The control gate line 40 is formed over the floating gate 34 and also controls the second section 37 of the channel region 36 to provide split-gate operation. The source region 38 is formed sufficiently far from the floating gate 34 so that the second section 37 of the channel region is controlled by the control gate 40, but does not have to be accurately defined.
With improvements in integrated circuit processing technology, the length of the channel region 36 may be reduced dramatically. One way to reduce the cell size is to use the stacked etch techniques described above with respect to the stacked gate cell 10. However, utilization of a stacked etch process for fabricating split-gate cells has two significant drawbacks. First, referring to the FIG. 2B plan view of the split-gate cell 30, because in the split-gate structure the poly 2 control lines and the poly 1 floating gates are perpendicular to one another, a stacked etch of the poly 2 and poly 1 layers can result in digging into the buried N+ regions between adjacent control lines, i.e. regions (1) in FIG. 2, because of the insufficient thickness of the gate oxide overlying these regions. Furthermore, as the distance between the adjacent buried N+ regions is reduced, the potential for reach-through from the N+ source region 38 to the N+ drain region 32 in the channel region between adjacent control lines, i.e. region (2) in FIG. 2B, also increases.
It would, therefore, be desirable to have available a method that utilizes stacked etch techniques for fabricating a split-gate EPROM cell, but which does not cause bit line interruption and which prevents bit line to bit line reach-through.